1. Field of the Invention
The present invention relates to electronic-circuit registers, and in particular, to the detection of soft errors in electronic-circuit registers.
2. Description of the Related Art
Some electronic circuits include registers. An electronic-circuit register typically includes one or more latches. A latch, as used herein, refers to a bi-stable electronic logic circuit, i.e., a logic circuit having two stable states, where the circuit can be used to store one bit of data. As is known in the art, multiple types of latches are possible, e.g., SR latches, D latches, and flip-flops. A flip-flop, as used herein, refers to a clocked latch, i.e., a latch circuit that updates its output at times indicated by an enabling clock signal. As is known in the art, multiple types of flip-flops are possible, e.g., JK flip-flops and D flip-flops. Some flip-flops are edge-triggered, updating their outputs on the uptick, i.e., rising edge, or downtick, i.e., falling edge, of the clock signal. Other flip-flops are level-enabled, updating their outputs for the duration that the clock signal is high or for the duration that the clock signal is low.
Registers are different from memory arrays. Similarly, flip-flops are different from the memory cells that make up memory arrays. In particular, flip-flops are different from non-volatile memory cells, such as read-only memory (ROM) cells, because flip-flops, unlike non-volatile memory cells, do not retain their stored values once they are powered down. Flip-flops are different from volatile memory cells, such as random-access memory (RAM) cells, in several ways. Flip-flops are different from dynamic RAM (DRAM) memory cells which need to be regularly refreshed, typically many times a second, to maintain their data, since flip-flops do not require such regular refreshing. RAM memory cells, both DRAM and static RAM (SRAM), are organized in memory arrays, where each RAM memory cell stores one bit of an addressable byte or word, while flip-flops are freestanding devices. To find out the value stored by a RAM memory cell, specialized read circuitry has to read the value of the byte or word that comprises that memory cell. The memory-reading process involves providing power on selected bit and word lines for conditional transmission to the read circuitry, where transmission is based on the values stored by the memory cells being read. A flip-flop, however, outputs its stored value without requiring specialized reading circuitry. Thus, a flip-flop, whenever it is powered up, outputs a signal that can drive another device, while a memory cell does not. Therefore, flip-flops tend to have faster access times than comparable-technology memory cells.
FIG. 1 shows circuit 100 comprising four rising-edge-triggered D flip-flops 101, 102, 103, and 104 having (i) signals 101a, 102a, 103a, and 104a, respectively, as D inputs and (ii) signal 105a as clock inputs. Circuit 100 further comprises AND gate 105, which serves to gate clock signal CLK. AND gate 105 has clock signal CLK and enable signal EN as inputs and signal 105a as an output. If enable signal EN is low, then signal 105a is low regardless of the state of clock signal CLK. If, however, enable signal EN is high, then signal 105a follows clock signal CLK. The data outputs of flip-flops are generally referred to herein as Q and Q outputs. The Q outputs of flips-flops 101 and 102, i.e., signals 101b and 102b, respectively, go into logic cloud 106, which contains zero or more logical circuits. Signals 103a and 104a, each of which depends in some way on one or both of signals 101b and 102b, are provided as D inputs to flip-flops 103 and 104, respectively, from logic cloud 106. Flip-flops 103 and 104 output signals 103b and 104b, respectively. Flip-flops 101, 102, 103, and 104 pass signals applied to their D inputs to their Q outputs (and inverted versions of these signals to their Q outputs) on rising edges of gated clock signal 105a. 
A flip-flop uses additional power whenever its clock input causes a data refresh. If the values stored in a flip-flop register remain substantially constant, then power usage can be reduced by conditionally gating (e.g., holding constant) the clock signal input to the register's flip-flops. For example, in circuit 100 of FIG. 1, signal 105a, applied to the clock inputs of the flip-flops, can be held constant by de-asserting (i.e., setting to low) enable signal EN. If the clock input is periodically held constant, then the flip-flops refresh less frequently and, consequently, use less power overall. If the flip-flops of circuit 100 do not need to be constantly refreshed, then this provides an opportunity to save energy on the operation of circuit 100. Thus, circuit 100 can use gate 105 to gate clock signal CLK in order to reduce the energy used by circuit 100.
Flip-flops such as those in circuit 100 are subject to soft errors, where transient conditions cause the stored bit's value to flip. One common cause of soft errors is cosmic radiation, where a cosmic ray strikes a flip-flop and creates a transient condition that provides sufficient energy to flip the stored bit. If a soft error occurs in a circuit whose clock signal is gated to save energy, then that error can remain for a relatively long time, thereby causing long-term and undetected provision of erroneous information within circuit 100.
One known method to mitigate the soft-error problem is to implement a hardened flip-flop, i.e., a flip-flop that is less likely than an un-hardened flip-flop to be affected by transient conditions and suffer a soft error. U.S. Pat. No. 3,786,282 to Orndorff, incorporated herein by reference in its entirety, describes a flip-flop hardened against soft errors by using “a capacitive memory in the cross coupled feedback loop of the flip flop circuit to drive the flip flop back to its pre-irradiation state” (Orndorff, Abstract).
U.S. Pat. No. 6,624,677 to Wissel, incorporated herein by reference in its entirety, describes a different scheme for a hardened flip-flop that comprises “a master latch circuit; a slave latch circuit coupled to the master latch circuit; and a correction circuit for increasing an amount of charge that can be absorbed by the master latch circuit in response to a soft-error event when the slave latch circuit is in a transparent phase and when both the master and slave latch circuits are storing the same data” (Wissel, Abstract). An additional technique mentioned in the Wissel patent for reducing the sensitivity of flip-flop circuits to soft errors includes increasing the physical size of the flip-flops, which makes the flip-flops less susceptible to soft errors from the impact of cosmic rays. Schemes for hardening flip-flops require additional physical space on a circuit where space is likely at a premium. In addition, hardened flip-flops can still suffer soft errors.
Another technique for dealing with soft errors is the implementation of redundant registers. One duplicate register set can indicate an error where corresponding flip-flops, i.e., a base flip-flop and a corresponding duplicate flip-flop, output different values. Soft errors can be corrected by using majority voting among trios of corresponding flip-flops, i.e., a base flip-flop and two corresponding duplicate flip-flops. For example, if one flip-flop in a trio suffers a soft error, the trio will still output the correct value because the other two corresponding flip-flops will have the correct value. This correct value can also be used to correct the flip-flop which suffered the soft error. Redundant registers and their attendant circuitry, however, take up a lot of additional physical space on a circuit where space is likely at a premium.